In order to achieve high-integration and high-speed, dimensions of semiconductor integrated circuits have been reduced, and various materials and techniques have been proposed and used during fabrication. For example, dual damascene technology and copper conductors are applied to reduce resistances and resistance-capacitance (RC) delay of interconnect structures in integrated circuits (ICs). As ICs are made smaller, and the distance between adjacent lines is reduced, low dielectric constant (low-k) dielectric materials are used in advanced copper interconnect technology to reduce these delays.
Interconnect structures of a semiconductor IC connect the various active devices and circuits of the IC to a plurality of conductive pads on the top surface of the die. Multi-level interconnect structures have been developed that accommodate the advances in active-device density by more effectively routing conductive paths between the active devices and the surface of the die. In typical IC designs, five or more individual interconnect levels of conductive paths may be used to accommodate the active-device density. Multi-level interconnect structures comprise metallization lines arranged in multiple layers (or levels). The metallization lines of each individual level are formed in an interlevel dielectric (ILD) material. The ILD electrically isolates the metallization lines from one another within each level of the interconnect structures and electrically isolates metallization lines in adjacent levels.
Damascene processes are routinely used in back-end-of-line (BEOL) processing for fabricating multi-level interconnect structures. In a damascene process, trenches and vias are etched in a layer of ILD and filled with a conductive material, such as copper (Cu) or a Cu-based alloy, to create conductive lines and vertical conductive paths between the interconnect lines in different levels.
The conductive paths of the multi-level interconnect structures terminate in bond pads at the surface of the IC. The bond pads are relatively large metal areas distributed throughout at least a top surface of the die. Bond pads are used to establish electrical contact between the integrated circuits and either a package substrate of an IC package or a probe pin (that is used for wafer acceptance testing, or WAT). The pads used during WAT are also referred to as, “process control monitor (PCM) pads.” A probe makes an electrical contact between a probe pin and the bond pads, so voltage or current can be applied to the IC for testing device functionality and performance. The bond pads that are used for WAT may be distributed in the scribe lines between dies. These scribe lines are severed during the die singulation process, with the cuts passing through the bond pads.
A conventional approach for configuring the WAT bond pads on the interconnect structure is to include bond pads in the scribe line on each interconnect layer, aligned beneath the bond pads in scribe line of the top metal layer, and to include metal-filled vias connecting the bond pads in each of the interconnect levels, aligned beneath each bonding pad or probe pad in the top metal layer. The bond pads in the first interconnect (M1) layer may be used for in situ testing before the second (M2) through top metal (MT) layers are formed.
The dicing (or singulation) process can produce a large mechanical stress, which may be dependent on numerous conditions, including: cut width, die saw speed, die saw temperature, die saw pressure, etc.
Conventional multi-level interconnect structures have been susceptible to failure due to cracking when the PCM pad is cut by a die saw. Experience has shown that during singulation, the dielectric in the scribe lines may crack in the vicinity of the bond pads, and that these cracks may propagate to the dies. This problem becomes more acute when low-k dielectric materials (including extreme low-k, ELK and ultra low-k, ULK) are used for the ILD material, because low-k dielectric materials are more brittle than high-k dielectrics.